This invention relates to a semiconductor element which permits easy performance of a test such as an operation checking, as well as an operation analysis and fault analysis.
As generally known, semiconductor elements are subjected to a test or an operation analysis or a fault analysis after manufacturing. With the advent of high density semiconductor elements such as those found in integrated circuits and LSI circuits, circuit formation elements such as diffusion layers, polysilicon layers and aluminium layers have become necessarily microminiaturized in their demension.
In order to perform the operation analysis and fault analysis, it has generally been necessary to measure a potential on an electrode by mechanically contacting an Au wire on the electrode to be measured. With the microminiaturization of semiconductor elements, corresponding electrodes have become finer and finer, making it impossible to bring the Au wire into contact with the electrode. Even if contact is made between the wire and the electrode, an effect resulting from a capacitance formed between the wire and an electrode cannot be disregarded.
An electron beam tester (abbreviated hereinafter to an EB tester) has been developed to improve such drawbacks. The EB tester is constructed as shown, for example, in FIG. 1. An electron gun 3 including a cathode 1 and a pulse beam generator 2 is disposed in an airtight container 4. A deflection lens 5 is disposed on an electron beam path to deflect electron beams emitted from the electron gun 3.
The surface of a semiconductor element 6 which is beforehand placed in the container is scanned by the electron beam deflected by the deflection lens 5. If this is done, secondary electrons 7 are emitted from the semiconductor element 6. The secondary electrons 7 are deflected by deflection means 8 disposed on the beam incident side of the semiconductor element 6, and fall on a secondary electron multiplying section 10 through a retarding grid 9 (one kind of an energy filter).
When the semiconductor element 6 is operated under a scanning electronic microscope (SEM) while using the EB tester, it is possible to obtain a contrast corresponding to the level of a potential. This is what is called "a voltage contrast" phenomenon. If the potential of the electrode is lower, more secondary electrons are emitted and thus a brighter image is observed. Such contrast is qualitative to an appreciable extent. When the secondary electrons thus emitted are measured through a retarding grid (energy filter) 9, it is possible to measure a potential fairly quantitatively. Suppose that the semiconductor element 6 is driven by a proper power source (not shown) from the outside. If in this case the voltage on the retarding grid 9 is properly selected, the voltage on the semiconductor element can be measured with an accuracy of about 30 mV.
A semiconductor element such as a dynamic random access memory (d-RAM) takes a multilayered structure as shown in FIGS. 2 and 3 and the following problem arises in making measurement by the EB tester. As shown in FIG. 2 a diffusion layer (a data line) is formed in the surface of a semiconductor substrate 22 and an insulating layer 24 is formed on that surface portion of the substrate 22 which is located in the neighborhood of the diffusion region 23. A field oxide film is formed at each side of a combined configuration of the insulating layer 24 and diffusion region (data line) 23. First and second polysilicon layers 27 and 28 are formed on the insulating layer 24 with an insulating layer 26 therebetween, the insulating layer 26 being formed by a chemical vapor deposition method or a sputtering method. An insulating film 29 is formed by a chemical vapor deposition method or a sputtering method on the electrode 28. An aluminium layer (word line) 30 is connected to the diffusion region 23 and an insulating layer 31 is formed on the surface including the aluminium layer 30.
As a result, an SiO.sub.2 layer of, for example, 2.4 .mu.m is formed on the diffusion region 23 and first polysilicon layer 27, an SiO.sub.2 of, for example, 1.8 .mu.m is formed on the second polysilicon layer 28, and an SiO.sub.2 layer of, for example, 1.0 .mu.m is formed on the aluminium layer 30. The insulating layers are thickly formed on the respective interconnection layers 27, 28 and 30 and semiconductor substrate 22 and diffusion region 23, respectively, with a varying thickness.
If this structure is observed by an EB tester under a voltage contrast, a potential signal amount from each interconnection layer is influenced by the thickness of the SiO.sub.2 layer covered on the interconnection layer. That is, the thicker the SiO.sub.2 layer becomes, the more the potential signal amount is decreased. Even if, for example, the respective layers are all at the same potential level, the potential signal amount and contrast of the respective layer will vary.
It is very difficult, and entirely impossible in a quantitative way, to measure the potentials of, for example, the semiconductor substrate 22, diffusion region 23 and polysilicon layers 27, 28 by the EB tester.